As is well known in the prior art, filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects (often referred to as a “Damascene” or a “Dual Damascene” process) requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface. As is also well known in the prior art, the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO2, SiOX, or SiOXNY); and (c) to be compatible with subsequent electroplating copper upon its surface.
As is well known, the requirement of providing a low-resistance electrical path is fulfilled by choosing the seed layer to be comprised of an adequately thick, low-resistivity material.
As is further well known, since copper has a rather poor adhesion to oxide surfaces, the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer. As is well known in the prior art, the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds). The barrier layer is often also referred to as an “adhesion layer” or a “liner”. In addition to providing good adhesion, the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device. As is well known in the prior art, the barrier layer is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials.
As is still further well known, the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper.
Typically, a seed layer comprises a copper layer that is deposited by a “dry” technique, such as by physical vapor deposition (“PVD”), including but not limited to sputtering, ion plating, or evaporation, or by chemical vapor deposition (“CVD”). However, the seed layer may also be deposited by a “wet” electroless plating process. In such cases, the copper seed layer thickness is typically in a range of about 300 Å to about 2,000 Å on the field (i.e., the top surface of the wafer outside trenches and via openings). In such cases, the barrier layer is typically deposited to a thickness of about 50 Å to about 500 Å (on the field) by either a PVD or a CVD technique.
The PVD techniques include, for example and without limitation, techniques such as evaporation, ion plating, and various sputtering techniques. Sputtering techniques include, for example and without limitation, techniques such as DC and/or RF plasma sputtering, bias sputtering, collimated sputtering, magnetron sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, or Ionized Metal Plasma (IMP) sputtering. As is well known in the art, in general, due to their anisotropic and directional (“line of sight”) nature, the PVD techniques produce non-conformal deposition. For a comprehensive description of sputtering techniques and their applications, see for example an article entitled “Sputter Deposition Processes” by R. Parsons, pp. 177–208 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). However, some of the PVD techniques (such as ion plating) may produce, under certain conditions, a relatively more conformal deposition. For a comprehensive description of the ion plating technique and its applications, see for example an article entitled “The Cathodic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 209–285 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). The CVD techniques include, for example and without limitation, thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), Atomic Layer CVD (“ALCVD”), and Metallo Organic CVD (“MOCVD”). Atomic Layer Deposition or Alternating Layer Deposition (ALD) is generally considered to be a CVD (ALCVD) technique, or a particular variant thereof. However, it is sometimes referred to as a class by its own. Similar to other CVD techniques, the ALD techniques include particular variants such as, for example, Thermal ALD, Low Pressure ALD (LPALD) and Radical Assisted or Plasma Enhanced ALD (PEALD). In general, the ALD techniques produce more conformal deposits, at lower deposition temperatures, than other CVD techniques. However, the ALD techniques are generally much slower than the other CVD techniques. As defined herein, the term “ALD” refers to (and includes) all variants of the ALD techniques, such as, for example and without limitation, Thermal ALD or ALCVD, Low Pressure ALD (LPALD) and Radical Assisted or Plasma Enhanced ALD (PEALD). For a comprehensive description of CVD techniques and their applications, see for example an article entitled “Thermal Chemical Vapor Deposition” by K. F. Jensen and W. Kern, pp. 283–368 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). For example, one precursor used for CVD Cu is Cupraselect™, which precursor is sold by Schumacher, Inc. Another precursor is Cu(II) hexafluoroacetylacetonate. The latter can be reacted with hydrogen gas to obtain high purity copper. As is well known in the art, in general, due to their isotropic and non-directional nature, the CVD (and ALD) and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings. However, under certain conditions, some of the CVD (and ALD) techniques (such as PECVD or PEALD) can be made to deposit less conformal or non-conformal layers.
Aspect ratio (“AR”) is typically defined as a ratio between a vertical dimension, D (depth), of an opening and its smallest lateral dimension, W (width, or diameter): AR=D/W. Usually, in electroplating metals or alloys to fill patterns having high aspect ratio openings (for example, in an insulator or a dielectric), the electroplating rate inside openings is slower than the rate outside openings (i.e., on the field). Further, the higher the AR of the openings, the slower the electroplating rate is inside. This results in poor or incomplete filling (voids) of high AR openings, when compared with results achieved with low AR openings. To overcome this problem in the prior art, commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill. Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating.
The openings may consist of vias, trenches, or patterned photoresist. As is well known, in damascene or dual damascene processes, an insulating or a dielectric layer is pattern-etched to form openings therein. Next, a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings. Next, copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings. Finally, excess plated copper overlying the openings and the top surface (the field) of the insulating layer, as well as the barrier and seed layers on the field, are removed, for example, by a mechanical polishing or by a chemical mechanical polishing (“CMP”) technique. The end result is copper filled openings (trenches and vias), including bottom and sidewall surfaces lined by the barrier and seed layers. In today's most advanced copper filling processes for trenches and vias, the openings have ARs as high as 7:1 (D=1.4 μm; W=0.2 μm). Future trenches and vias openings will likely require W=0.10–0.13 μm, or narrower, and AR=8:1–20:1, or larger.
As semiconductor device dimensions continue to shrink, there is an ever increasing demand for narrower interconnect cross-sections and, thus, smaller openings and larger aspect ratios (AR) during the copper electrofill. To ensure void-free copper filling, the seed layer inside the openings must completely cover the bottom and the sidewall surfaces inside the openings without discontinuities, or else there will be voids in the copper electrofill. On the other hand, the seed layer must not be so thick on the sidewalls that it pinches-off or seals the very narrow openings and should not overhang the top corners of the openings. It should leave enough room inside the small openings for a successive electrofilling step. In contrast to these requirements with respect to the openings, the seed layer must be sufficiently thick on the top surface (the field) to provide a low-resistive electrical path that facilitates uniform plating across the surface of the wafer. That is, the seed layer must be sufficiently thick (for example, a Cu seed layer thickness is preferably at least about 1,000 Å) on the field to avoid radial non-uniformity across the wafer caused by a voltage (or IR) drop between a contact at the edge of the wafer to the center of the wafer. Any voltage drop (and resulting non-uniformity therefrom) becomes more severe with increasing wafer size (200 mm to 300 mm), and as the resistance of the seed layer increases due to insufficient thickness and/or high resistivity. To ensure a sufficiently low-resistance seed layer, it is now common to deposit a copper seed layer to a thickness of about 1,000 Å to about 2,000 Å on the top surface (field) by a PVD technique. However, the typical conformal seed layer thickness of about 300 Å to about 800 Å (on the field), deposited by the CVD or electroless techniques, may not be sufficient.
Neither of these techniques satisfies all of the above-identified requirements. The non-conformal PVD techniques, while providing adequate thickness on the field, fail to provide continuous and complete sidewall and/or bottom coverage inside very narrow openings with large AR. They also result in substantial overhangs at the top corners of the openings. The conformal techniques (such as CVD, ALD, or electroless), on the other hand, while providing continuous and complete sidewalls and bottom coverage of the seed layer inside very narrow openings, pinch-off or seal the small openings when used at thicknesses required on the field for a low-resistance electrical path. As a result, typical conformal seed layers are too thin on the field and too thick inside the very narrow openings.
As one can readily appreciate from the above, a need exists in the art for a method and apparatus to produce a continuous seed layer on the sidewalls and bottom of the openings, while maintaining sufficient thickness on the field to facilitate good uniformity across the wafer and void-free copper electrochemical filling of very narrow openings having high aspect ratios.